Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis

Field-Programmable Gate Array (FPGA)-based Software-Defined Radio (SDR) is well-suited for experimenting with advanced wireless communication systems, as it allows to alter the architecture promptly while obtaining high performance. However, programming the FPGA using a Hardware Description Language (HDL) is a time-consuming task for FPGA developers and difficult for software developers, which limits the potential of SDR. High-Level Synthesis (HLS) tools aid the designers by allowing them to program on a higher layer of abstraction. However, if not carefully designed, it may lead to a degradation in computing performance or significant increase in resource utilization. This work shows that it is feasible to design modern Orthogonal Frequency Division Multiplex (OFDM) baseband processing modules like channel estimation and equalization using HLS without sacrificing performance and to integrate them in an HDL design to form a fully-operational FPGA-based Wi-Fi (IEEE 802.11a/g/n) transceiver. Starting from no HLS experience, a design with minor overhead in terms of latency and resource utilization as compared to the HDL approach was created in less than one month. We show the readability of the sequential logic as coded in HLS, and discuss the lessons learned from the approach taken and the benefits it brings for further design and experimentation. The FPGA design generated by HLS was verified to be bit-true with its MATLAB implementation in simulation. Furthermore, we show its practical performance when deployed on a System-on-Chip (SoC)-based SDR using a professional wireless connectivity tester.Comment: 7 pages, extended version of poster accepted at FCCM 202

Het sociale media netwerk van NPO Spirit in beeld: Resultaten van het project TeSMeN: Televisie en Sociale Media Netwerken

Van oorsprong worden televisieprogramma’s op een lineaire manier aangeboden aan kijkers: een omroep bepaalt in welke volgorde programma’s worden getoond. Dit verandert echter langzaam. Ondemand mogelijkheden via internet en settopboxen zorgen ervoor dat kijkers zelf kunnen bepalen wanneer ze welk programma willen kijken. De Nederlandse Publieke Omroep (NPO) speelt op die mogelijkheden in met onder meer de dienst Uitzending Gemist, een NPOapplicatie voor mobiele apparaten en verschillende themakanalen. Eén van die themakanalen is NPO Spirit. Ze biedt via internet ondemand video’s aan op het gebied van levensbeschouwing, spiritualiteit en diversiteit. Het aanbod is zo pluriform mogelijk. Dat wil zeggen dat verschillende religies en levensbeschouwingen naast elkaar worden aangeboden. NPO Spirit formuleert haar propositie dan ook als volgt: “NPO Spirit laat de kijker genieten en brengt op toegankelijke wijze (nieuwe) inzichten!" De uiteindelijke doelstelling van dit project is om méér mensen en meer verschillende groepen te bereiken. Het eindresultaat bestaat uit (1) een specifiek overzicht voor NPO Spirit van relevante trefwoorden, groepen ( hubs ) en sleutelfiguren ( influencers ) op internet, en (2) een algemene werkwijze om vanuit een organisatie of merk te bepalen welke groepen, trefwoorden en sleutelfiguren op het internet relevant zijn. Dit moet ertoe leiden dat NPO Spirit beter in staat raakt om video’s naar consumenten ‘toe te brengen’

Accelerating FPGA-based Wi-Fi transceiver design and prototyping by high-level synthesis

Field-Programmable Gate Array (FPGA)-based Software-Defined Radio (SDR) is well-suited for experimenting with advanced wireless communication systems, as it allows to alter the architecture promptly while obtaining high performance. However, programming the FPGA using a Hardware Description Language (HDL) is a time-consuming task for FPGA developers and difficult for software developers, which limits the potential of SDR. High-Level Synthesis (HLS) tools aid the designers by allowing them to program on a higher layer of abstraction. However, if not carefully designed, it may lead to a degradation in computing performance or significant increase in resource utilization. This work shows that it is feasible to design modern Orthogonal Frequency Division Multiplex (OFDM) baseband processing modules like channel estimation and equalization using HLS without sacrificing performance and to integrate them in an HDL design to form a fully-operational FPGA-based Wi-Fi (IEEE 802.11a/g/n) transceiver. Starting from no HLS experience, a design with limited overhead in terms of latency and resource utilization as compared to the HDL approach was created in less than one month. The FPGA design generated by HLS achieved the same performance as compared to its HDL counterpart when deployed on a System-on-Chip (SoC)-based SDR, as verified by a professional wireless connectivity tester

WIP : achieving self-interference-free operation on SDR platform with critical TDD turnaround time

Software Defined Radio (SDR) platforms are valuable for research and development activities or high-end systems that demand real-time adaptable wireless protocols. While low latency can be achieved using the dedicated digital processing unit of a state-of-the-art SDR platform, its Radio Frequency (RF) front-end often poses a limitation in terms of turnaround time (TT), the time needed for switching from the receiving to the transmitting mode (or vice versa). Zero Intermediate Frequency (ZIF) transceivers are favorable for SDR, but suffer from self-interference even if the device is not currently transmitting. The strict MAC-layer requirements of Time Division Duplex (TDD) protocols like Wi-Fi cannot be achieved using configurable ZIF transceivers without having to compromise receiver sensitivity. Using a novel approach, we show that the TT using the AD9361 RF front-end can be as low as 640 ns, while the self-interference is at the same level as achieved by the conventional TDD mode, which has a TT of at least 55 μs. As compared to Frequency Division Duplex (FDD) mode, a decrease of receiver noise floor by about 13 dB in the 2.4 GHz band and by about 4.5 dB in the 5 GHz band is achieved

Improved TDD operation on Software-Defined Radio platforms towards future wireless standards

Software-Defined Radio (SDR) platforms are valuable for research and development activities or high-end systems that demand flexible wireless protocols. While low-latency digital baseband processing can be achieved using a dedicated processing unit, like an FPGA or hardware accelerator, its multi-purpose Radio Frequency (RF) front-end often poses a limitation. Zero Intermediate Frequency (ZIF) transceivers are favorable for SDR, however, even for Time Division Duplex (TDD) systems, these transceivers suffer from self-interference when the transmitting and receiving Local Oscillator (LO) is set to the same frequency. To achieve low self-interference, switching from receiving to transmitting mode is needed. However, the time this takes (turnaround time, TT) for configurable RF front-ends often violates the strict timing requirements of protocols like Wi-Fi and 5G, which require response times in the order of microseconds. In this work, we first evaluate the advantages and disadvantages of several methods to suppress self-interference of a ZIF transceiver. Next, a novel approach is proposed, which can reduce the TT to as low as 640 ns using the widely used AD9361 configurable ZIF RF front-end, while the noise floor is at the same level as achieved by the conventional way of switching between transmit and receive mode. We have realized and validated this approach using openwifi - an open-source Wi-Fi implementation on SDR. As a result, the receiver sensitivity is improved by up to 17 dB in the 2.4 GHz band and 9.5 dB in the 5 GHz band, for over-the-air transmissions